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Three dimensional hybrid wafer scale integration using the GE high density interconnect technology
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2002
Year
Unknown Venue
EngineeringDevice IntegrationMultichip ModuleIntegrated CircuitsInterconnect (Integrated Circuits)Wafer Scale ProcessingAdvanced Packaging (Semiconductors)NanoelectronicsElectronic Packaging3D Ic ArchitectureElectrical EngineeringOverlay TechnologyComputer EngineeringMicroelectronicsAdvanced PackagingThree-dimensional Heterogeneous IntegrationApplied PhysicsGe High DensityThree-dimensional Multichip Technology3D Integration
A three-dimensional multichip technology is discussed. It provides solutions to the interconnect and packaging problems associated with very high density requirements of large distributed processing systems and large solid-state memory systems. The technical approach involves an extension of the 2D multichip module (MCM) circuits fabricated with the high-density-interconnect (HDI) overlay technology. These are then stacked and interconnected with a modified version of the 2D HDI interconnect process applied to the side edges of the stack. Test structures and a stack of function circuit circuits are fabricated and tested. The features of this approach, a description of the process, and the results of tests on the demonstration vehicles are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>