2002 · 12 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsClock ManagementIntegrated Circuit DesignLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationTiming AnalysisClock MultiplicationFrequency SynthesisHigh-speed Circuit DesignHigh-speed Cmos DesignPower ConsumptionPower Consumption OptimizationSelf-aligned ProcessesSettling Time
This paper presents a high-speed multi-modulus prescaler IC which consists of nine stages of dual-modulus prescaler (+2/+3) connected in cascade. The multi-modulus prescaler divides the input clock frequency by an integer between 512 to 1024 with a unit step increment. Two kinds of prescaler ICs have been developed: one operates up to 1.2 GHz with a dissipation of 10.8 mW at 2.7 V, and the other operates up to 2.2 GHz with a dissipation of 19.2 mW at 2.7 V. The lower power consumption is achieved by using super self-aligned process technology and by minimizing the critical path delays of the circuits. These prescaler ICs will be applied to a programmable divider for a synthesizer which needs a fast-settling time.
2
A 20 ps/G Si Bipolar IC Using Advanced SST with Collector Ion Implantation
Shinsuke Konaka, Yoshihito Amemiya, K. Sakuma et al. · 1987 · 55 citations
A 3 mW 1.0 GHz silicon ECL dual-modulus prescaler IC
M. Mizuno, H. Suzuki, M. Ogawa et al. · 2003 · 10 citations
Engineering, Computer Engineering, Electrical Engineering +17