A method for simulation of floating-gate UV-programmable circuits with application to three new 2-MOSFET digital circuits

Abstract

We present some fundamental aspects on how UV-programmed floating-gate (FGUVMOS) circuits may be simulated using the AIM-Spice or Eldo simulators and the BSIM3v3 model. We introduce ways of implementing FGUVMOS binary logic simpler than previously reported. Reduction in transistor and capacitor count for some simple NAND and NOR gates are from three to two MOSFETs, and four to three capacitors, respectively. We also show some aspects of a reconfigurable two-transistor circuit capable of computing the CARRY' function for a FULL-ADDER using two MOSFETs, which is more than 90 percent reduction in transistor count compared to earlier reported FGUVMOS circuits.