IEEE International Workshop on System-on-Chip for Real-Time Applications · 2004 · 26 citations · 6 references
ComputingComputer EngineeringComputer ScienceComputer ArchitectureComputer NetworksInterconnection NetworksNetwork ArchitectureNetwork Performance AnalysisNetwork-on-chip DesignPerformance ModelingReal-time Systems DesignSystem SimulationBottleneck DetectionNetwork BenchmarkingNetwork SimulationNetwork-on-chipNetwork-on-chip ArchitecturesOn-chip InterconnectsOn-chip NetworksSimulation Environment Design
Networks are becoming increasingly popular for use as on-chip interconnects. The problems with specification and performance evaluation increase with these solutions compared to the traditional interconnect. This paper describes the design and simulation environment developed in the SoCBUS network-on-chip project. This environment is used as a basis to develop the benchmarking procedures necessary to assess the performance of the networks. Two benchmarking examples are presented and used for evaluation of the SoCBUS network. These examples show how the simulation environment can be used to find the load bottleneck. They also show the appropriateness of the SoCBUS solution for (hard) real-time systems.
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William J. Dally, Brian Towles · 2001 · 3.2K citations
Engineering, Computer Engineering, Electrical Engineering +17
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Kgw Kees Goossens, P. Wielage, A. Peeters et al. · TU/e Research Portal · 2002 · 124 citations
Cost-performance trade-offs in networks on chip: a simulation-based approach
S.G. Pestana, E. Rijpkema, A. Rădulescu et al. · 2004 · 88 citations
Design of a switching node (router) for on-chip networks
Sathe, Wiklund, Liu · 2003 · 30 citations
Engineering, Computer Engineering, Electrical Engineering +17