Design of a switching node (router) for on-chip networks

Abstract

Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional interconnects, such as on-chip networks (OCN), must be used. Our OCN is capable of providing a data transfer throughput of 19.2 Gbps/link. The key element of our OCN is the switching node. We present a prototype design of a 5-input, 5-output, scalable switching node. The switching node is constructed from a collection of parameterizable and reusable hardware blocks, and is a basic building block of our OCN. The switching node is characterized by an area of 0.06 mm sq. and a frequency of 1.2 GHz in 0.18 micron CMOS technology.