Constant voltage stress induced degradation in HfO2/SiO2 gate dielectric stacks

Abstract

Defect generation in HfO2/SiO2 gate dielectric stacks under constant voltage stress is investigated. It is found that the stress induced electrical degradation in HfO2/SiO2 stacks is different than in the SiO2 layer. The variation of the gate leakage current with different polarities shows different degradation characteristics after stress. Positive charge generation is also observed under both negative and positive gate voltage polarities. These degradation phenomena are explained by the composite effect of three components: neutral trap generation, electron trapping, and positive charge generation in the gate stacks.