Design-oriented characterization of CMOS over the continuum of inversion level and channel length

Abstract

A methodology for small signal characterization of CMOS processes over the full range of inversion level and channel length is presented. Measured transconductance and output conductance of a 0.5 /spl mu/m standard CMOS process are presented from deep weak inversion to deep strong inversion for both NMOS and PMOS devices for channel lengths ranging from 0.5 /spl mu/m to 33.4 /spl mu/m. The data is presented in normalized form permitting device evaluation at any inversion level, channel length, and drain current. This characterization is useful for modern analog CMOS design anywhere in the continuum of inversion level and channel length. This method furthermore presents a novel and rigorous benchmark for evaluating the accuracy of compact MOS models. Initial results are given illustrating EKV MOS model transconductance accuracy. The characterization methodology can be extended to deeper submicron processes addressing the increasing uncertainty in small signal parameter values and MOS model accuracy.