1985 · 21 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignIntegrated Circuit DesignTiming AnalysisGate Array DesignHigh-speed Cmos DesignMacro-based DesignMultiplier Design
This paper will cover a 2500-gate bipolar array with 80ps delay, which uses a macro cell design and 1μ rules. A 7.5ns 16b multiplier has been realized.
2
A GaAs 16 × 16b parallel multiplier using self alignment technology
Y. Nakayama, K. Suyama, Haruo Shimizu et al. · 1983 · 23 citations
Engineering, Computer Engineering, Electrical Engineering +10