Embedded glass interposer for heterogeneous multi-chip integration

Abstract

Interposer technology has been developed for providing a fine line/space and high density interconnections that cannot be matched by current laminate substrate technology. Interposer materials such as silicon, glass and organic had been under intensive development. We have been developing EIC (Embedded Interposer Carrier) technology which eliminates the interconnection between the interposer and the underneath organic substrate [1, 2]. This could provide a lower profile, good electrical performance, and do not change the current industry infrastructure. Besides silicon, there are various advantages in using glass as interposer; such as low loss characteristic in high frequency, high degree of flatness for fine line patterning and adjustable CTE to lower the stress of heterogeneous package structure. Moreover, the potential of producing glass interposer in large panel format enables glass interposer to be more cost effective solution comparing to Silicon interposer. In this study, an EIC substrate with embedded glass interposer for flip chip assembly is demonstrated. Glass interposers with size of 21×14 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 100 μm thickness, through glass vias (TGV) of 30 μm diameter, and line/space of 3 μm/3 μm were produced. Subsequently, the glass interposer was embedded in built-up dielectric materials to form the EIC substrate. Multi-layers dielectrics were built up with filled blind vias and RDL patterns to fan-out the circuits from the embedded glass interposer. The production of EIC was conducted in a 508 mm×508 mm panel using standard printed circuit board production line. Later, special designed Si chips to mimic the AP (application processor, 2,904 I/O in 9×9 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and wide I/O chips (1,200 I/Os in 10×10 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) were flip-chip bonded to the EIC substrate via joints of 40 μm pitch Cu pillars and micro solder bump to form an integrated module.