Channel masking synthesis for efficient on-chip test compression

Abstract

The effectiveness of on-product test compression methods is degraded by the capture of unknown logic states ("X-states") by the scan elements. This work describes a simple but cost-effective solution called channel masking that masks the X-states and allows test compression methods to be widely deployed on a variety of designs. It also discusses various aspects of the channel masking hardware and the synthesis and validation methodology to support its use in a typical design flow. Results are presented to show its effectiveness on some large industrial designs.