2002 · 21 citations · 2 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMicroelectronicsSystem-on-chip DesignAccelerator ArchitectureArithmetic FunctionsDigital Signal ProcessingField-programmable Gate Array ArchitectureHardware AccelerationTiming AnalysisArithmetic Logic Unit ArchitectureArithmetic Unit DesignConvolutionFast Fourier TransformMatrix MultiplicationMultiplier DesignMultiply-accumulate UnitsPost-processing
A chip for real-time computation of 256-, 512- and 1024-point Fourier-transforms uses architecture targeting frequency-domain convolution of real-valued 1024/spl times/1024 data-sets at 5 Frames/s. Compared to existing FFT-designs, the processor also supports element-wise matrix multiplication (MUL) and dedicated pre- and post-processing steps required for simultaneous transformation of two real-valued sequences with one complex FFT (cf. real-valued FFT). In addition, considering the large dynamic numerical range required for 2D frequency-domain convolution, the ALU-arithmetic is based on twos complement data-sets represented with 64b (2/spl times/32) complex mantissa and an additional 8b exponent. Under nominal conditions of 20/spl deg/C room temperature and 3.3 V power supply, the ALU computes a complex 1024-pt FFT within 80 /spl mu/s.
2
Handbook for digital signal processing
Choice Reviews Online · 1993 · 77 citations
Engineering, Computer Engineering, Electrical Engineering +10