European Solid-State Circuits Conference · 2000 · 26 citations · 0 references
EngineeringElectrical EngineeringMicroelectronicsMicrowave EngineeringSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyHigh-frequency Semiconductor DevicesIntegrated Circuit DesignOscillatorsRadio-frequency Integrated CircuitsBicmos TechnologyCmos OscillatorsCmos Radio-frequency CircuitsNegative Resistance OscillatorsNoise In Metal-oxide-semiconductor Field-effect TransistorsPhase NoiseRf Cmos DesignSige Bicmos Design
This paper examines the effect of the choice of MOS varactor on the performance of a CMOS negative resistance oscillator. The three most common MOS varactor structures (inversion, accumulation, and gated varactor) are combined with a spiral inductor over either deep trench oxide or a polysilicon patterned ground shield, to implement a matrix of six LC VCO's in a 0.24-µm (0.18- µm L eff ) SiGe BiCMOS technology[1]. Typical measured VCO phase noise is -119.7 dBc/Hz at a 1-MHz offset from a 5.67-GHz carrier, while drawing 1.6 mA from a 1.5-V supply, for a VCO figure of merit of-191 dBc/Hz.