Publication | Closed Access
A 50ns DSP with parallel processing architecture
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1987
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Unknown Venue
EngineeringParallel Processing ArchitectureComputer ArchitectureSystem-level DesignInterconnection Network ArchitectureIntegrated CircuitsHigh-performance ArchitectureI/o BottlenecksParallel ComputingInstruction-level ParallelismTechnology Co-optimizationComputer EngineeringHigh-speed NetworkingComputer ScienceMicroelectronicsHardware AccelerationVlsi ArchitectureParallel ProcessingParallel ProgrammingProgrammable DspTwo-level Hierarchy
This report will cover a programmable DSP that avoids I/O bottlenecks through a two-level hierarchy of instructions. The IC contains 430K transistors on a 149mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die.