1990 · 19 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignConfigurable Logic BlocksDevice ScalingLow-power Digital Circuit DesignMemory DevicesMemory Subsystem DesignBicmos TechnologyDynamic Power DissipationLow-power Memory ArchitectureLow-power Memory CircuitsMemory Circuit DesignPower-efficient Memory DesignSense Amplifier DesignUltra-low-power Cmos
A 256 K-word*4-b emitter-coupled-logic (ECL) RAM fabricated by means of 0.8- mu m BiCMOS technology is described. The memory has an address access time of 6.5 ns with active power dissipation of 800 mW at 80 MHz. The memory utilizes a 41- mu m/sup 2/ NMOS four-transistor memory cell, 2-row and 16-column redundancy, a wired-OR sense amplifier, and an improved ECL CMOS level converter to achieve 6.5-ns access time with an ECL 10 K interface. To improve yield for a high-density RAM, a flexible redundancy scheme is necessary. The 2-row and 16-column redundant array increases the number of usable devices at least fivefold compared with a previously reported scheme.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>