A 256K flash EEPROM using triple polysilicon technology - Concepedia

Concepedia

Publication | Closed Access

A 256K flash EEPROM using triple polysilicon technology

31

Citations

0

References

1985

Year

F. Masuoka, Masafumi Asano, H. Iwahashi, T. Komuro, Shin‐ichi Tanaka

Unknown Venue

Hardware SecurityElectrical EngineeringChip SizeEngineeringSingle Transistor CellTriple Polysilicon TechnologyFlash MemoryComputer EngineeringComputer ArchitectureSemiconductor MemoryMicroelectronicsOptoelectronics

Abstract

This report will cover a 256K Flash Electrically Erasable PROM with a single transistor cell. Chip size of 5.7×5.8mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was achieved by using 2.0μ design rules and triple polysilicon technology.