Partial silicides technology for tunable work function electrodes on high-k gate dielectrics - fermi level pinning controlled PtS/sub X/, for HfO/sub X/(N) pMOSFET

Abstract

We investigate an origin of the Fermi-level pinning at the gate electrode/HfO/sub x/(N) interface, and propose a new technology for tuning the work function with a partial silicidation of Pt on HfO/sub x/ (N). It is clearly shown that the effective work functions (/spl Phi/ /sub m,eff/) of fully silicided (FUSI) NiSi and PtSi on HfO/sub x/(N) are rigidly fixed due to the Fermi-level pinning, and that the impurity doping does not help changing /spl Phi/ /sub m,eff/ at all. The large flatband voltage (VFB) shifts of FUSI PtSi MOSFETs have been observed irrespective of Si deposition processes. On the basis of these new findings, nMOSFET with pinned n+poly-Si and pMOSFET with partially pinned PtSi on HfO/sub x/ (N) for a balanced CMOS have been proposed, and both of them have shown good electrical properties. Furthermore, it is experimentally discussed that the control of the Si atom content at the PtSi/sub x//HfO/sub 2/ interface is a key factor to relax the pinning effect. The partial silicidation technology will be a most feasible method for advanced metal gate CMOS.