High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package

Abstract

In this paper, we firstly propose the high frequency equivalent circuit model of the chip-to-chip vertical via based on its physical configuration. The model parameters are extracted from the measurement of S-parameters using a vector network analyzer up to 20GHz frequency range. The proposed circuit model is verified experimentally in frequency and time domains. Furthermore, the high frequency characteristics of the chip-to-chip vertical via are investigated.