Design and implementation of the POWER5/spl trade/ microprocessor

J. Clabes, J. Friedrich, M. Sweet, J. DiLullo, Sam Chu, D. Plass, J. L. Dawson, Paul Muench, Larry Powell, Michael S. Floyd,

2004 · 23 citations · 1 references

Concepts

Abstract

POWER5 offers /spl sim/4/spl times/ performance over the previous design by incorporating simultaneous multithreading, a latency-optimized memory subsystem, extensive reliability, availability and serviceability (RAS), and power management support. The 276M-transistor processor is implemented in a 0.13 /spl mu/m, 8M silicon-on-insulator technology and operates above 1.5 GHz.

References

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