Memory Latency Optimization is a design methodology within memory hierarchy architecture that specifically targets the reduction of the time delay between a memory request and the availability of data, distinguishing it from broader performance enhancement techniques by its exclusive focus on minimizing access latency at various levels of the memory hierarchy.
324
Publications
15.8K
Citations
987
Authors
243
Institutions
Publications per year
2017–2026
93
Parents
Publications
324
1–5 of 324
Authors
987
- OM
15
h-index
- HH
8
h-index
- MK
8
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- MP
6
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- EH
6
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1–5 of 987
Institutions
243
Carnegie Mellon University
Pittsburgh, United States
17 h-index
58 publications
5.8K citations
Intel (United States)
Santa Clara, United States
16 h-index
38 publications
3.5K citations
The University of Texas at Austin
Austin, United States
12 h-index
31 publications
3K citations
ETH Zurich
Zurich, Switzerland
11 h-index
37 publications
2.1K citations
Pennsylvania State University
State College, United States
9 h-index
30 publications
787 citations
Stanford University
Stanford, United States
8 h-index
15 publications
773 citations
Korea Advanced Institute of Science and Technology
Daejeon, South Korea
8 h-index
31 publications
935 citations
Georgia Institute of Technology
Atlanta, United States
7 h-index
27 publications
960 citations
1–8 of 243
Venues
- ACM SIGARCH Computer Architecture News
10 publications · 585 citations
10
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- IEEE Transactions on Computers
8 publications · 233 citations
8
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- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
6 publications · 129 citations
7
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- IEEE Transactions on Parallel and Distributed Systems
TPDS · 5 publications · 159 citations
6
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- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
4 publications · 102 citations
4
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1–5