Publication | Closed Access
Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing
288
Citations
23
References
2010
Year
Unknown Venue
Non-volatile MemoryEngineeringComputer ArchitecturePhase Change MemoryRead LatencyMulti-channel Memory ArchitectureHardware SecurityHigh-performance ArchitectureRead PerformanceMemorySystems EngineeringParallel ComputingPhase-change MemoryElectrical EngineeringElectronic MemoryComputer EngineeringComputer ScienceMemory ArchitectureWrite LatencyEdge ComputingCloud ComputingPhase Change MemoriesParallel ProgrammingWrite CancellationTransactional Memory
Phase Change Memory (PCM) is a promising main‑memory technology, but its write latency is much higher than read latency, and scheduled writes can still delay subsequent reads even when buffers are used. The authors aim to reduce read latency in PCM systems when write requests interfere with reads. They propose adaptive Write Cancellation, which aborts a scheduled write if a read arrives within a set window, and Write Pausing, which pauses at the end of each write iteration to service pending reads. These policies cut the read‑latency increase by 75 % and boost overall system performance by 46 % on average, with minimal hardware changes.
Phase Change Memory (PCM) is emerging as a promising technology to build large-scale main memory systems in a cost-effective manner. A characteristic of PCM is that it has write latency much higher than read latency. A higher write latency can typically be tolerated using buffers. However, once a write request is scheduled for service to a bank, it can still cause increased latency for later arriving read requests to the same bank. We show that for the baseline PCM system with read-priority scheduling, the write requests increase the effective read latency to 2.3x (on average), causing significant performance degradation. To reduce the read latency of PCM devices under such scenarios, we propose adaptive Write Cancellation policies. Such policies can abort the processing of a scheduled write requests if a read request arrives to the same bank within a predetermined period. We also propose Write Pausing, which exploits the iterative write algorithms used in PCM to pause at the end of each write iteration to service any pending reads. For the baseline system, the proposed technique removes 75% of the latency increase incurred by read requests and improves overall system performance by 46% (on average), while requiring negligible hardware and simple extensions to PCM controller.
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