Comparison and analysis of delay elements

Abstract

This paper comprehensively reviews ten different delay element architectures for use in CMOS VLSI design. They can be categorized into three separate families: transmission gate based, cascaded inverter based, and voltage-controlled based. Six of these delay elements are already in use and we propose four new ones. We compare these delay elements, both analytically and using simulations, in terms of four important parameters: delay, signal integrity, power consumption, and area, and find that they have widely varying characteristics. The results presented in this paper, expressed as parameter ranges, will enable a designer to select the most appropriate delay element that meets delay, signal integrity, power consumption, and area specifications.