Publication | Closed Access
A sub-0.1 μm circuit design with substrate-over-biasing [CMOS logic]
17
Citations
6
References
2002
Year
Unknown Venue
Electrical EngineeringEngineeringVlsi DesignCircuit SystemMicrofabricationBias Temperature InstabilityMixed-signal Integrated CircuitGate-substrate Tie CircuitryComputer EngineeringComputer ArchitectureDownward TrendGate DelayMicroelectronicsElectronic Circuit
A substrate-over-biasing technique together with gate-substrate tie circuitry continues the downward trend of gate delay and reduces power for sub-0.1 /spl mu/m LSIs.
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