Connecting the physical and application level towards grasping aging effects

Abstract

Technology scaling noticeably increases the susceptibility of transistors to varied degradations induced by aging phenomena like Bias Temperature Instability (BTI) and Time-Dependent-Dielectric Breakdown (TDDB). Therefore, estimating the reliability of an entire computational system necessitates investigating how such phenomena will ultimately lead to failures - considering that aging starts from the physical level and ends up at the application level, where workloads (i.e. software programs) run. The key challenge is that an accurate estimation imposes analyzing the impact of aging on each individual transistor within a sophisticated on-chip system using complex physics-based models. The latter requires both a careful experimental model parameter derivation for calibration and precise information regarding the actual temperature voltage-stress waveforms that may be applied to the transistors during lifetime. These waveforms are directly driven by the running workloads creating the inevitable necessity to connect the physical and application level. As a matter of fact, this challenge is exacerbated in the nano era, due to the typical workloads (i.e. multiple applications running in parallel along with an operating system) that may run on top of a tremendous number of transistors. This paper investigates this challenge to provide designers with an abstracted, yet sufficiently accurate reliability estimation that takes into account the interrelations between the physical and application level towards grasping how aging actually degrades the reliability of on-chip systems.