A novel nickel SALICIDE process technology for CMOS devices with sub-40 nm physical gate length

Abstract

A novel nickel self-aligned silicide (SALICIDE) process technology has been developed for CMOS devices with physical gate length of sub-40 nm. The excess silicidation problem due to edge effect is effectively solved by using a low-temperature, in-situ formed Ni-rich silicide. With this new process, excess poly gate silicidation is prevented. Island diode leakage current and breakdown voltage are also improved.