Circuit performance of double-gate SOI CMOS

Abstract

The paper presents the performance of double-gate MOSFETs (DG MOSFET) in the circuit design perspective is examined via simulation using device structures based on the ITRS specification. The propagation delay (t/sub pd/) and energy dissipation of DG CMOS inverter chains with different number of fan-out (FO) are investigated. Load capacitors are added to the output node of each inverter to simulate the parasitic wiring capacitance (C/sub int/) between two stages, assuming reasonable input time and output loading capacitance. The performance result showed superiority of SDG device (symmetric double-gate device) over ADG device (asymmetric double-gate device) in speed and energy efficiency. Performance evaluation indicates that SDG SOI CMOS is the promising device for next generation high performance CMOS technology.