Partial response detection technique for driver power reduction in high speed memory-to-processor communications

Abstract

A partial-response detection technique cuts the driver power by up to 85% in memory-to-processor communication with several hundred MHz data rates. The signaling scheme reduces driver power by reducing the transistor width and raising the termination resistance above the the characteristic impedance. This results in a reduction of the signal bandwidth and thus a large inter-symbol interference (ISI). This side effect is offset by detecting the partial response of the transmitted signal, in which the ISI is subtracted from the signal. The receiver samples the data at half-periods of the clock. It employs a delay-locked loop to time sampling at the end of each symbol period of length T, to fully exploit signal current integrated in the signaling line during that period.