An eight channel 35 GSample/s CMOS timing analyzer

Abstract

While today's test systems measure inputs at a single time point each cycle, measuring when the inputs arrive is often more useful for understanding timing and jitter problems. An eight channel system is used to explore the feasibility of such a time measuring tester front-end. This system achieves 27.8 ps timing resolution in a 0.25 /spl mu/m CMOS technology using an oversampled architecture with 40 phase-shifted clocks that span a 900 MHz cycle. The chip contains two clock generators, eight input channels, on-chip memory and histogram hardware.