Low-jitter process-independent DLL and PLL based on self-biased techniques

TLDR

The authors present DLL and PLL designs that employ self‑biased techniques. The designs set damping factor and bandwidth‑to‑frequency ratio through a capacitance ratio and generate all internal bias voltages via self‑biasing, eliminating external bias circuits. The DLL and PLL achieve process‑technology independence, fixed damping and bandwidth ratios, broad frequency coverage, input‑phase‑offset cancellation, and low input‑tracking jitter; the fabricated PLL operates from 0.0025 MHz to 550 MHz with 384 ps jitter at 250 MHz under 500 mV supply noise.

Abstract

Delay-locked loop (DLL) and phase-locked loop (PLL) designs based upon self-biased techniques are presented. The DLL and PLL designs achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly, low input tracking jitter. Both the damping factor and the bandwidth to operating frequency ratio are determined completely by a ratio of capacitances. Self-biasing avoids the necessity for external biasing, which can require special bandgap bias circuits, by generating all of the internal bias voltages and currents from each other so that the bias levels are completely determined by the operating conditions. Fabricated in a 0.5-/spl mu/m N-well CMOS gate array process, the PLL achieves an operating frequency range of 0.0025 MHz to 550 MHz and input tracking jitter of 384 ps at 250 MHz with 500 mV of low frequency square wave supply noise.