64 Mb 6.8 ns random ROW access DRAM macro for ASICs

Abstract

With the emerging huge demand for multimedia applications, even personal computers have come to require enhanced memory systems, especially for 3D graphics, MPEG encoding, and image/voice recognition. While the large memory bandwidth of Rambus DRAMs and Synchronous DRAMs offers high-speed data transfer and large capacity, they fall short in terms of low latency. Despite the efforts made by many programmers to circumvent the effects of the high latency of DRAM access, memory access instructions continue to accumulate, which limits system performance. The many conditional branch/jump operations of mixed multi-media applications (e.g., MPEG-4), for example, make such attempts at circumvention almost completely impossible. In fact, both lower random access latency and larger bandwidth are actually more pressing requirements for the latest memory systems. In response to this situation, this 6.8ns random ROW access DRAM macro has 64Mb capacity and 9.1ns complete random access cycle. This high-speed random access DRAM macro for ASICs, is to be combined with logics for 3D graphics, MPEG encoding, and image/voice recognition to create compact, low-power, high-performance LSIs for multimedia applications.