Wafer cost reduction through design of high performance fully silicided ESD devices

Abstract

A universal technique to design cost effective, fully silicided, high performance ESD devices is introduced. This novel design solution can be implemented in a straightforward manner without process modifications. ESD performance levels obtained in different 0.25 /spl mu/m and 0.18 /spl mu/m CMOS technologies demonstrate that this technique can successfully replace silicide-blocked devices to achieve good ESD performance levels with economical silicon real estate consumption. In addition, a novel multi-finger turn-on design technique, which can be applied to both fully silicided and silicide blocked designs is presented.