Write Latency Optimization is a performance-enhancement methodology in solid-state storage systems that specifically reduces the time delay between the initiation of a write operation and its completion by improving data programming, caching, or scheduling mechanisms.
165
Publications
6.5K
Citations
537
Authors
173
Institutions
Publications per year
2017–2026
44
Parents
Publications
165
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Guangyu Sun, Xiangyu Dong, Yuan Xie et al. · 2009 · 439 citations
Russell Sears, Raghu Ramakrishnan · 2012 · 311 citations
Adwait Jog, Asit Mishra, Cong Xu et al. · 2012 · 254 citations
1–5 of 165
Authors
537
- MB
8
h-index
- FO
8
h-index
- RB
7
h-index
- YX
7
h-index
- CR
6
h-index
1–5 of 537
Institutions
173
Pennsylvania State University
State College, United States
11 h-index
47 publications
4K citations
University of Pittsburgh
Pittsburgh, United States
11 h-index
42 publications
1.7K citations
Huazhong University of Science and Technology
Wuhan, China
10 h-index
44 publications
796 citations
Karlsruhe Institute of Technology
Karlsruhe, Germany
8 h-index
33 publications
837 citations
Wuhan National Laboratory for Optoelectronics
Wuhan, China
7 h-index
26 publications
366 citations
IBM (United States)
Armonk, United States
5 h-index
14 publications
1.2K citations
Seoul National University
Seoul, South Korea
4 h-index
13 publications
300 citations
Arizona State University
Tempe, United States
4 h-index
11 publications
186 citations
1–8 of 173
Venues
- IEEE Transactions on Computers
7 publications · 149 citations
7
h-index
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
5 publications · 86 citations
5
h-index
- ACM SIGARCH Computer Architecture News
3 publications · 202 citations
3
h-index
- IEEE Transactions on Knowledge and Data Engineering
TKDE · 3 publications · 38 citations
3
h-index
- Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014
Conference · 3 publications · 44 citations
3
h-index
1–5