Tri-state Buffering
Tri-State Buffering is a digital circuit design technique that belongs to the category of signal transmission mechanisms, distinguished by its ability to exhibit three distinct output states—logical high, logical low, and high-impedance—thereby enabling multiple devices to share a common bus without electrical interference.
14
Publications
887
Citations
45
Authors
19
Institutions
Publications per year
2017–2026
3
Variants
Three-state Buffering
Parents
14
An experimental 1.5-V 64-Mb DRAM
Y. Nakagome, Hiroki Tanaka, Kazuhiro Takeuchi et al. · IEEE Journal of Solid-State Circuits · 1991 · 182 citations
Engineering, Computer Engineering, Electrical Engineering +17
Vaughn Betz, Jonathan Rose · 1999 · 168 citations
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Delhi Technological University
New Delhi, India
3 h-index
7 publications
97 citations

University of Toronto
Toronto, Canada
2 h-index
4 publications
440 citations

Hanyang University
Seoul, South Korea
1 h-index
2 publications
36 citations
Space Micro (United States)
San Diego, United States
1 h-index
1 publications
201 citations
Shikoku (Japan)
Marugame, Japan
1 h-index
1 publications
182 citations
S.N. Bose National Centre for Basic Sciences
Kolkata, India
1 h-index
2 publications
28 citations
Samsung (South Korea)
Seoul, South Korea
1 h-index
1 publications
45 citations

National Institute of Technology Jamshedpur
Jamshedpur, India
1 h-index
1 publications
19 citations
1–8 of 19
2 publications · 32 citations
2
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1 publications · 201 citations
1
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1 publications · 12 citations
1
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OQE · 1 publications · 19 citations
1
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1 publications · 18 citations
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