Transaction-level Modeling

Transaction-Level Modeling is a hardware modeling methodology within Register-Transfer Level design that abstracts system behavior by focusing on the transfer of data and control information between components as discrete transactions, rather than on signal transitions or clock cycles.

269

Publications

12.2K

Citations

560

Authors

275

Institutions

Publications per year

2017–2026

49

Authors

560

  1. NB
    Nicola Bombieri

    University of Verona, Italy

    16 publications · 367 citations

    12

    h-index

  2. RD
    Rolf Drechsler

    University of Bremen, Germany

    10 publications · 226 citations

    10

    h-index

  3. FF
    Franco Fummi

    University of Verona, Italy

    13 publications · 267 citations

    10

    h-index

  4. GP
    Graziano Pravadelli

    University of Verona, Italy

    10 publications · 261 citations

    10

    h-index

  5. RD
    Rainer Dömer

    University of California, Irvine, United States

    9 publications · 239 citations

    9

    h-index

1–5 of 560

Venues

  1. SSRN Electronic Journal

    Repository · 27 publications · 1.1K citations

    17

    h-index

  2. Design, Automation, and Test in Europe

    Conference · 6 publications · 151 citations

    6

    h-index

  3. 2008 Design, Automation and Test in Europe

    Conference · 5 publications · 96 citations

    5

    h-index

  4. 5

    h-index

  5. Management Science

    5 publications · 135 citations

    5

    h-index

1–5