Transaction-level Modeling
Transaction-Level Modeling is a hardware modeling methodology within Register-Transfer Level design that abstracts system behavior by focusing on the transfer of data and control information between components as discrete transactions, rather than on signal transitions or clock cycles.
269
Publications
12.2K
Citations
560
Authors
275
Institutions
Publications per year
2017–2026
49
Variants
Tlm
269
Lukai Cai, Daniel D. Gajski · 2003 · 527 citations
Shu Tian-Cole, John L. Crompton, Victor L. Willson · Journal of Leisure Research · 2002 · 379 citations
Entrusted loans: A close look at China's shadow banking system
Franklin Allen, Yiming Qian, Guoqian Tu et al. · Journal of Financial Economics · 2019 · 356 citations · Full text
Business, Finance, Real Estate +10
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275
University of California, Irvine
Irvine, United States
18 h-index
54 publications
3.1K citations
University of Verona
Verona, Italy
12 h-index
47 publications
1.1K citations
University of Bremen
Bremen, Germany
10 h-index
27 publications
544 citations

Centre National de la Recherche Scientifique
Paris, France
7 h-index
19 publications
535 citations
University of California, Berkeley
Berkeley, United States
7 h-index
13 publications
434 citations
STMicroelectronics (France)
Montrouge, France
7 h-index
11 publications
450 citations
University of Stuttgart
Stuttgart, Germany
6 h-index
15 publications
260 citations
Columbia University
New York, United States
6 h-index
10 publications
355 citations
1–8 of 275
Repository · 27 publications · 1.1K citations
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Conference · 6 publications · 151 citations
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Conference · 5 publications · 96 citations
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5 publications · 158 citations
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5 publications · 135 citations
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