Temporal Logic Assertions is a formal method in assertion-based verification that employs temporal logic to specify and verify dynamic properties of hardware or software systems over time, distinguishing it from static assertion techniques by explicitly capturing temporal sequences and timing constraints.
110
Publications
5.1K
Citations
271
Authors
137
Institutions
Publications per year
2017–2026
21
Parents
Publications
110
1–5 of 110
Authors
271
- GF
8
h-index
- GE
6
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- PA
6
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- GP
5
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- ZZ
5
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1–5 of 271
Institutions
137
Arizona State University
Tempe, United States
7 h-index
23 publications
691 citations
Ludwig-Maximilians-Universität München
Munich, Germany
6 h-index
7 publications
140 citations
University of Verona
Verona, Italy
5 h-index
14 publications
510 citations
National Institute of Informatics
Tokyo, Japan
5 h-index
7 publications
164 citations
National Institute of Advanced Industrial Science and Technology
Tsukuba, Japan
4 h-index
6 publications
130 citations
Toyota Motor Corporation (Switzerland)
Safenwil, Switzerland
3 h-index
4 publications
241 citations
University of Tübingen
Tübingen, Germany
3 h-index
16 publications
185 citations
The University of Texas at Austin
Austin, United States
3 h-index
5 publications
408 citations
1–8 of 137
Venues
- EPiC series in computing
6 publications · 126 citations
6
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- Theoretical Computer Science
3 publications · 682 citations
3
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- IEEE Transactions on Computers
2 publications · 104 citations
2
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- Design, Automation, and Test in Europe
Conference · 2 publications · 47 citations
2
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- Journal of Systems and Software
JSS · 2 publications · 106 citations
2
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