Concepedia

Scalar Instructions

Scalar Instructions is an instruction set architecture concept that belongs to the class of machine instructions, distinguished by operating on single data elements at a time as opposed to vectors or aggregates, thereby performing one operation per instruction cycle on individual scalar values.

44

Publications

2K

Citations

134

Authors

57

Institutions

Publications per year

2017–2026

6

Parents

Publications

44

Highly concurrent scalar processing

Ping‐Yu Hsu, Edward S. Davidson · ACM SIGARCH Computer Architecture News · 1986 · 235 citations · Full text

, , +17

Optimizing Compiler for the CELL Processor

Alexandre E. Eichenbergert, Kathryn O’Brien, Kevin O’Brien et al. · 2005 · 173 citations

, , +17

Using advanced compiler technology to exploit the performance of the Cell Broadband Engine™ architecture

Alexandre E. Eichenberger, John O’Brien, Kathryn O’Brien et al. · IBM Systems Journal · 2006 · 151 citations

, , +17

Compiler optimization of scalar value communication between speculative threads

Antonia Zhai, Christopher B. Colohan, J. Gregory Steffan et al. · 2002 · 130 citations

, , +17

Superword-Level Parallelism in the Presence of Control Flow

Jaewook Shin, Mary Hall, Jacqueline Chame · 2005 · 127 citations

, , +13

1–5 of 44

Authors

134

  1. VP
    Vasileios Porpodas

    University of Edinburgh, United Kingdom

    4 publications · 90 citations

    4

    h-index

  2. MV
    Mateo Valero

    Universitat Politècnica de Catalunya, Spain

    3 publications · 94 citations

    3

    h-index

  3. LF
    Luís F. W. Góes

    Pontifícia Universidade Católica de Minas Gerais, Brazil

    2 publications · 36 citations

    2

    h-index

  4. BS
    Byoungro So

    University of Southern California, United States

    2 publications · 324 citations

    2

    h-index

  5. SA
    Saman Amarasinghe

    Massachusetts Institute of Technology, United States

    2 publications · 49 citations

    2

    h-index

1–5 of 134

Institutions

57

  1. IBM (United States)

    Armonk, United States

    4 h-index

    5 publications

    798 citations

  2. Universitat Politècnica de Catalunya

    Barcelona, Spain

    4 h-index

    10 publications

    266 citations

  3. Intel (United States)

    Santa Clara, United States

    3 h-index

    4 publications

    84 citations

  4. Georgia Institute of Technology

    Atlanta, United States

    3 h-index

    3 publications

    336 citations

  5. University of Edinburgh

    Edinburgh, United Kingdom

    2 h-index

    2 publications

    36 citations

  6. Pontifícia Universidade Católica de Minas Gerais

    Belo Horizonte, Brazil

    2 h-index

    2 publications

    36 citations

  7. University of Oslo

    Oslo, Norway

    2 h-index

    2 publications

    121 citations

  8. Carnegie Mellon University

    Pittsburgh, United States

    2 h-index

    5 publications

    546 citations

1–8 of 57

Venues

  1. ACM SIGARCH Computer Architecture News

    3 publications · 346 citations

    3

    h-index

  2. ACM Transactions on Architecture and Code Optimization

    TACO · 2 publications · 49 citations

    2

    h-index

  3. Proceedings of the VLDB Endowment

    PVLDB · 1 publications · 30 citations

    1

    h-index

  4. Design, Automation, and Test in Europe

    Conference · 1 publications · 10 citations

    1

    h-index

  5. IEEE Transactions on Consumer Electronics

    1 publications · 10 citations

    1

    h-index

1–5