Reset Sequence Design

Reset Sequence Design is a methodological framework in embedded processor integration that specifies the controlled, deterministic initialization of processor states and peripheral configurations to ensure reliable system startup under defined hardware and software constraints.

11

Publications

412

Citations

46

Authors

15

Institutions

Publications per year

2017–2026

0

Authors

46

  1. HU
    Hasan Ural

    University of Ottawa, Canada

    2 publications · 47 citations

    2

    h-index

  2. RM
    Robert M. Hierons

    Brunel University of London, United Kingdom

    2 publications · 49 citations

    2

    h-index

  3. TD
    Thierry Ducourant

    Siemens (Germany), Germany

    1 publications · 29 citations

    1

    h-index

  4. LX
    Lihua Xie

    Nanyang Technological University, Singapore

    1 publications · 86 citations

    1

    h-index

  5. YT
    Yoshimichi Takano

    Japan Broadcasting Corporation (Japan), Japan

    1 publications · 27 citations

    1

    h-index

1–5 of 46

Venues

  1. Information Processing Letters

    2 publications · 52 citations

    2

    h-index

  2. ScholarWorks@UMassAmherst (University of Massachusetts Amherst)

    Repository · 1 publications · 10 citations

    1

    h-index

  3. Automatica

    1 publications · 86 citations

    1

    h-index

  4. IEEE Journal of Solid-State Circuits

    1 publications · 27 citations

    1

    h-index

  5. Automated Software Engineering

    1 publications · 22 citations

    1

    h-index

1–5