Concepedia

Register-transfer Level Security Verification

Register-Transfer Level Security Verification is a formal methodology within hardware security verification that analyzes and ensures the absence of security vulnerabilities in digital circuits by examining data flow and control logic transformations at the register-transfer level, distinguishing it from lower-level gate-based or higher-level architectural verification approaches.

12

Publications

406

Citations

50

Authors

13

Institutions

Publications per year

2017–2026

10

Parents

Publications

12

Register transfer level information flow tracking for provably secure hardware design

Armaiti Ardeshiricham, Wei Hu, Joshua Marxen et al. · 2017 · 129 citations

, , +17

QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment

Xiaolong Guo, Raj Gautam Dutta, Jiaji He et al. · 2019 · 48 citations

, , +13

Enhancing security via provably trustworthy hardware intellectual property

Eric Love, Yier Jin, Yiorgos Makris · 2011 · 36 citations

, , +16

RTL-ConTest: Concolic Testing on RTL for Detecting Security Vulnerabilities

Xingyu Meng, Shamik Kundu, Arun K. Kanuparthi et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2021 · 29 citations

, , +17

An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors

Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller et al. · IEEE Transactions on Computers · 2022 · 29 citations · Full text

, , +15

1–5 of 12

Authors

50

  1. FF
    Farimah Farahmandi

    University of Florida, United States

    3 publications · 49 citations

    3

    h-index

  2. YJ
    Yier Jin

    University of Central Florida, United States

    2 publications · 84 citations

    2

    h-index

  3. DS
    Dominik Stoffel

    University of Kaiserslautern, Germany

    2 publications · 40 citations

    2

    h-index

  4. MR
    Mohammad Rahmani Fadiheh

    University of Kaiserslautern, Germany

    2 publications · 40 citations

    2

    h-index

  5. WK
    Wolfgang Kunz

    University of Kaiserslautern, Germany

    2 publications · 40 citations

    2

    h-index

1–5 of 50

Institutions

13

  1. University of Florida

    Gainesville, United States

    5 h-index

    21 publications

    552 citations

  2. Intel (United States)

    Santa Clara, United States

    3 h-index

    5 publications

    121 citations

  3. University of Kaiserslautern

    Kaiserslautern, Germany

    2 h-index

    10 publications

    200 citations

  4. The University of Texas at Dallas

    Richardson, United States

    1 h-index

    3 publications

    87 citations

  5. Karlsruhe Institute of Technology

    Karlsruhe, Germany

    1 h-index

    3 publications

    54 citations

  6. Siemens (Germany)

    Munich, Germany

    1 h-index

    1 publications

    29 citations

  7. New York University

    New York, United States

    1 h-index

    2 publications

    56 citations

  8. Indian Institute of Technology Guwahati

    Guwahati, India

    1 h-index

    2 publications

    56 citations

1–8 of 13

Venues

  1. ACM Journal on Emerging Technologies in Computing Systems

    JETC · 2 publications · 46 citations

    2

    h-index

  2. 1

    h-index

  3. Journal of Electronic Testing

    JETTA · 1 publications · 18 citations

    1

    h-index

  4. IEEE Transactions on Computers

    1 publications · 29 citations

    1

    h-index

1–4