Hardware Security Verification

Hardware Security Verification is a formal methodology within hardware security that systematically assesses integrated circuits, chip designs, or hardware implementations to ensure their conformance to specified security properties and to detect vulnerabilities, trojans, or unintended behaviors that could compromise confidentiality, integrity, or availability.

412

Publications

20K

Citations

1.1K

Authors

343

Institutions

Publications per year

2017–2026

209

Authors

1.1K

  1. RK
    Ryan Kastner

    University of California San Diego, United States

    15 publications · 743 citations

    14

    h-index

  2. YJ
    Yier Jin

    University of Central Florida, United States

    15 publications · 689 citations

    14

    h-index

  3. RK
    Ramesh Karri

    New York University, United States

    14 publications · 781 citations

    13

    h-index

  4. GE
    G. Edward Suh

    Cornell University, United States

    12 publications · 1K citations

    12

    h-index

  5. MT
    Mark Tehranipoor

    University of Florida, United States

    9 publications · 362 citations

    10

    h-index

1–5 of 1.1K

Venues

  1. 11

    h-index

  2. 11

    h-index

  3. 9

    h-index

  4. arXiv (Cornell University)

    Repository · 7 publications · 189 citations

    7

    h-index

  5. 7

    h-index

1–5