Concepedia

Cache Side-channel Verification

Cache Side-Channel Verification is a formal method for analyzing hardware designs to detect and mitigate information leakage through shared cache resources by exploiting timing variations induced by cache access patterns.

4

Publications

163

Citations

16

Authors

6

Institutions

Publications per year

2017–2026

2

Parents

Publications

4

CaSym: Cache Aware Symbolic Execution for Side Channel Detection and Mitigation

Robert Brotzman, Shen Liu, Danfeng Zhang et al. · 2019 · 69 citations · Full text

, , +16

Ascon hardware implementations and side-channel evaluation

Erich Wenger, Christoph Dobraunig, Christoph Ehrenhöfer · Microprocessors and Microsystems · 2016 · 53 citations

, , +14

CANAL: a cache timing analysis framework via LLVM transformation

Chungha Sung, Brandon Paulsen, Chao Wang · 2018 · 31 citations

, , +17

Formally Verified Implementation of an Idealized Model of Virtualization

Gilles Barthe, Gustavo Betarte, Juan Diego Campo et al. · DROPS (Schloss Dagstuhl – Leibniz Center for Informatics) · 2014 · 10 citations · Full text

, , +11

1–4 of 4

Authors

16

  1. EW
    Erich Wenger

    Graz University of Technology, Austria

    1 publications · 53 citations

    1

    h-index

  2. CE
    Christoph Ehrenhöfer

    Graz University of Technology, Austria

    1 publications · 53 citations

    1

    h-index

  3. GB
    Gustavo Betarte

    Universidad de la República de Uruguay, Uruguay

    1 publications · 10 citations

    1

    h-index

  4. SL
    Shen Liu

    Pennsylvania State University, United States

    1 publications · 69 citations

    1

    h-index

  5. CS
    Chungha Sung

    University of Southern California, United States

    1 publications · 31 citations

    1

    h-index

1–5 of 16

Institutions

6

  1. University of Minho

    Braga, Portugal

    1 h-index

    1 publications

    10 citations

  2. Chalmers University of Technology

    Gothenburg, Sweden

    1 h-index

    1 publications

    10 citations

  3. Pennsylvania State University

    State College, United States

    1 h-index

    5 publications

    345 citations

  4. University of Southern California

    Los Angeles, United States

    1 h-index

    3 publications

    93 citations

  5. Graz University of Technology

    Graz, Austria

    1 h-index

    3 publications

    159 citations

  6. Universidad de la República de Uruguay

    Montevideo, Uruguay

    1 h-index

    3 publications

    30 citations

1–6 of 6

Venues

  1. DROPS (Schloss Dagstuhl – Leibniz Center for Informatics)

    Repository · 1 publications · 10 citations

    1

    h-index

  2. Microprocessors and Microsystems

    MICPRO · 1 publications · 53 citations

    1

    h-index

1–2