Redundancy Layout is a systematic methodology in Very-Large-Scale Integration design that incorporates duplicate circuit elements or interconnect structures to enhance yield, reliability, or fault tolerance by enabling functional substitution in the presence of defects or failures.
18
Publications
757
Citations
56
Authors
24
Institutions
Publications per year
2017–2026
1
Publications
18
Redundant-via enhanced maze routing for yield improvement
Gang Xu, Lida Huang, David Z. Pan et al. · 2005 · 88 citations
Computing, Computational Engineering, Algorithmic Design +16
1–5 of 18
Authors
56
- DZ
3
h-index
- LH
2
h-index
- KH
2
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- KA
1
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- AK
1
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1–5 of 56
Institutions
24
The University of Texas at Austin
Austin, United States
3 h-index
7 publications
382 citations
IBM (United States)
Armonk, United States
3 h-index
4 publications
255 citations
University of Illinois Urbana-Champaign
Urbana, United States
2 h-index
2 publications
143 citations
Texas Instruments (United States)
Dallas, United States
2 h-index
2 publications
143 citations
Hitachi (Japan)
Tokyo, Japan
1 h-index
11 publications
209 citations
Cirrus Logic (United States)
Austin, United States
1 h-index
2 publications
36 citations
The Ohio State University
Columbus, United States
1 h-index
2 publications
28 citations
Ontario Tech University
Oshawa, Canada
1 h-index
2 publications
50 citations
1–8 of 24
Venues
- Purdue e-Pubs (Purdue University System)
Repository · 2 publications · 50 citations
2
h-index
- IEEE Transactions on Computers
2 publications · 108 citations
2
h-index
- IEEE Journal of Solid-State Circuits
2 publications · 216 citations
2
h-index
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
1 publications · 37 citations
1
h-index
- International Journal of Flexible Manufacturing Systems
1 publications · 14 citations
1
h-index
1–5