Parameterized Delay Modeling
Parameterized Delay Modeling is a formal delay modeling approach that belongs to the class of analytical delay models and is distinguished by its explicit incorporation of variable parameters to characterize circuit or system timing behavior under diverse operating conditions.
10
Publications
680
Citations
22
Authors
12
Institutions
Publications per year
2017–2026
1
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10
Luca Daniel, O.C. Siong, L.S. Chay et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2004 · 342 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17
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Czech Technical University in Prague
Prague, Czechia
2 h-index
4 publications
120 citations
University of California, Berkeley
Berkeley, United States
2 h-index
2 publications
185 citations

Makerere University
Kampala, Uganda
1 h-index
2 publications
62 citations
Carnegie Mellon University
Pittsburgh, United States
1 h-index
1 publications
16 citations
Defence Science and Technology Agency
Singapore, Singapore
1 h-index
1 publications
342 citations

University of Toronto
Toronto, Canada
1 h-index
2 publications
24 citations
Uganda Christian University
Mukono, Uganda
1 h-index
1 publications
31 citations
National University of Singapore
Singapore, Singapore
1 h-index
3 publications
1K citations
1–8 of 12
1 publications · 10 citations
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JSS · 1 publications · 10 citations
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1 publications · 31 citations
1
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1 publications · 24 citations
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Conference · 1 publications · 106 citations
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