Parameter Declaration

Parameter Declaration is a syntactic construct in Verilog that belongs to the category of compile-time constants, distinguished by its use in defining modifiable, named values that parameterize module interfaces and behavior to enable design reusability and configurability.

9

Publications

776

Citations

23

Authors

18

Institutions

Publications per year

2017–2026

1

Authors

23

  1. JB
    Jesse B. Wright

    IBM Research - Thomas J. Watson Research Center, United States

    1 publications · 54 citations

    1

    h-index

  2. HK
    Hans‐Jörg Kreowski

    University of Bremen, Germany

    1 publications · 54 citations

    1

    h-index

  3. KA
    K. Allaart

    Vrije Universiteit Amsterdam, Netherlands

    1 publications · 39 citations

    1

    h-index

  4. JW
    J. W. Thatcher

    IBM (United States), United States

    1 publications · 54 citations

    1

    h-index

  5. HE
    Hartmut Ehrig

    Technische Universität Berlin, Germany

    1 publications · 54 citations

    1

    h-index

1–5 of 23

Venues

  1. IEEE Transactions on Software Engineering

    TSE · 1 publications · 216 citations

    1

    h-index

  2. Ocean Engineering

    1 publications · 28 citations

    1

    h-index

  3. Computer Physics Communications

    1 publications · 152 citations

    1

    h-index

  4. Nuclear Physics A

    1 publications · 39 citations

    1

    h-index

  5. Journal of Object-oriented Programming

    1 publications · 12 citations

    1

    h-index

1–5