Parameter Declaration
Parameter Declaration is a syntactic construct in Verilog that belongs to the category of compile-time constants, distinguished by its use in defining modifiable, named values that parameterize module interfaces and behavior to enable design reusability and configurability.
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2017–2026
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Joseph A. Goguen · IEEE Transactions on Software Engineering · 1984 · 216 citations
Jeffrey R. Lewis, John Launchbury, Erik Meijer et al. · 2000 · 154 citations · Full text
Extension of HPL to complex arguments
D. Maître · Computer Physics Communications · 2011 · 152 citations · Full text
Parameter passing in algebraic specification languages
Hartmut Ehrig, Hans‐Jörg Kreowski, J. W. Thatcher et al. · Theoretical Computer Science · 1983 · 54 citations
Computing, Computer Science, Algebra +10
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IBM Research - Thomas J. Watson Research Center, United States
1 publications · 54 citations
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Télécom Paris
Palaiseau, France
1 h-index
3 publications
39 citations
École Normale Supérieure - PSL
Paris, France
1 h-index
1 publications
13 citations
Université Paris-Saclay
Gif-sur-Yvette, France
1 h-index
3 publications
39 citations
University of Delaware
Newark, United States
1 h-index
3 publications
324 citations
IBM (United States)
Armonk, United States
1 h-index
3 publications
162 citations
Menlo School
Atherton, United States
1 h-index
1 publications
216 citations
Université de Lille
Lille, France
1 h-index
1 publications
13 citations

University College Cork
Cork, Ireland
1 h-index
2 publications
56 citations
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TSE · 1 publications · 216 citations
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1 publications · 28 citations
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1 publications · 152 citations
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1 publications · 39 citations
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1 publications · 12 citations
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