Memory Layout Optimization is a computational strategy within the domain of data structure design that specifically refines the spatial arrangement of nodes in a skip list to minimize memory access latency and improve cache coherence during traversal operations.
138
Publications
6K
Citations
456
Authors
164
Institutions
Publications per year
2017–2026
25
Parents
Publications
138
Bowen Alpern, C. R. Attanasio, John Barton et al. · IBM Systems Journal · 2000 · 578 citations
A design for high-performance flash disks
Andrew Birrell, Michael Isard, Chuck Thacker et al. · ACM SIGOPS Operating Systems Review · 2007 · 188 citations
Rishi Kapoor, George Porter, Malveeka Tewari et al. · 2012 · 188 citations
1–5 of 138
Authors
456
- MK
5
h-index
- XS
3
h-index
- TC
3
h-index
- BW
3
h-index
- MH
3
h-index
1–5 of 456
Institutions
164
Carnegie Mellon University
Pittsburgh, United States
6 h-index
10 publications
839 citations
Google (United States)
Mountain View, United States
5 h-index
5 publications
357 citations
Microsoft (United States)
Redmond, United States
4 h-index
8 publications
982 citations
University of Wisconsin–Madison
Madison, United States
4 h-index
7 publications
676 citations
University of Stuttgart
Stuttgart, Germany
4 h-index
18 publications
270 citations
University of Waterloo
Waterloo, Canada
4 h-index
5 publications
176 citations
Pennsylvania State University
State College, United States
4 h-index
9 publications
151 citations
University of Toronto
Toronto, Canada
3 h-index
3 publications
86 citations
1–8 of 164
Venues
- IEEE Transactions on Computers
4 publications · 61 citations
4
h-index
- arXiv (Cornell University)
Repository · 4 publications · 78 citations
4
h-index
- IEEE Transactions on Parallel and Distributed Systems
TPDS · 3 publications · 109 citations
3
h-index
- ACM SIGOPS Operating Systems Review
3 publications · 219 citations
3
h-index
- ACM SIGARCH Computer Architecture News
3 publications · 207 citations
3
h-index
1–5