Concepedia

Mask Rule Checking

Mask Rule Checking is a verification methodology in integrated circuit design that ensures mask layouts comply with a set of geometric and process-specific constraints to guarantee manufacturability and performance.

15

Publications

349

Citations

75

Authors

23

Institutions

Publications per year

2017–2026

1

Parents

Publications

15

Pixel-based OPC optimization based on conjugate gradients

Xu Ma, Gonzalo R. Arce · Optics Express · 2011 · 76 citations · Full text

, , +15

Design rule checking and analysis of IC mask designs

B. W. Lindsay, Bryan Preas · 1976 · 45 citations · Full text

, , +13

An integrated mask artwork analysis system

T. Mitsuhashi, Toshiaki Chiba, Makoto Takashima et al. · 1980 · 42 citations

, , +13

Fast source mask co-optimization method for high-NA EUV lithography

Ziqi Li, Lisong Dong, Xu Ma et al. · Opto-Electronic Advances · 2024 · 33 citations · Full text

, , +16

CRITIC - an integrated circuit design rule checking program

Lawrence M. Rosenberg, Carole Benbassat · Design Automation Conference · 1974 · 23 citations

, , +12

1–5 of 15

Authors

75

  1. AT
    Alexander Tritchkov

    Mentor Technologies, United States

    2 publications · 36 citations

    2

    h-index

  2. KG
    Keith Gronlund

    ASML (Netherlands), Netherlands

    1 publications · 13 citations

    1

    h-index

  3. SD
    Stephen D. H. Hsu

    University of Oregon, United States

    1 publications · 13 citations

    1

    h-index

  4. HR
    H. Rombeek

    Bell (Canada), Canada

    1 publications · 13 citations

    1

    h-index

  5. SB
    Stanislas Baron

    Philips (France), France

    1 publications · 13 citations

    1

    h-index

1–5 of 75

Institutions

23

  1. Mentor Technologies

    Tulsa, United States

    3 h-index

    8 publications

    104 citations

  2. Bell (Canada)

    Montreal, Canada

    2 h-index

    4 publications

    49 citations

  3. CEA Grenoble

    Grenoble, France

    1 h-index

    1 publications

    13 citations

  4. NEC (Japan)

    Tokyo, Japan

    1 h-index

    5 publications

    65 citations

  5. University of Southampton

    Southampton, United Kingdom

    1 h-index

    2 publications

    30 citations

  6. Philips (France)

    Suresnes, France

    1 h-index

    4 publications

    52 citations

  7. Toshiba (Japan)

    Tokyo, Japan

    1 h-index

    1 publications

    42 citations

  8. United Monolithic Semiconductor (France)

    Villebon-sur-Yvette, France

    1 h-index

    2 publications

    26 citations

1–8 of 23

Venues

  1. 4

    h-index

  2. Design Automation Conference

    Conference · 3 publications · 48 citations

    3

    h-index

  3. Optical Microlithography XVIII

    1 publications · 13 citations

    1

    h-index

  4. Optics Express

    1 publications · 76 citations

    1

    h-index

  5. Bell System Technical Journal

    BSTJ · 1 publications · 20 citations

    1

    h-index

1–5