Interconnect Verification
Interconnect Verification is a formal method within the domain of Network-on-Chip design that systematically ensures the correctness, reliability, and functional integrity of on-chip communication architectures by validating their structural and behavioral properties against specified requirements.
32
Publications
998
Citations
100
Authors
53
Institutions
Publications per year
2017–2026
2
Parents
32
Design, Synthesis, and Test of Networks on Chips
Partha Pratim Pande, Cristian Grecu, A. Ivanov et al. · IEEE Design & Test of Computers · 2005 · 175 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17
Verifying IP-core based system-on-chip designs
Pankaj Chauhan, E. M. Clarke, Yao Lu et al. · 2003 · 53 citations
1–5 of 32
100
Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France
3 publications · 54 citations
3
h-index
3
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3
h-index
2
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2
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1–5 of 100
53
Techniques of Informatics and Microelectronics for Integrated Systems Architecture
Grenoble, France
3 h-index
8 publications
151 citations

Radboud University Nijmegen
Nijmegen, The Netherlands
2 h-index
2 publications
40 citations

University of Manchester
Manchester, United Kingdom
2 h-index
2 publications
62 citations

Centre National de la Recherche Scientifique
Paris, France
2 h-index
5 publications
58 citations

Université Grenoble Alpes
Saint-Martin-d'Hères, France
2 h-index
5 publications
58 citations

Université Joseph Fourier
Grenoble, France
2 h-index
5 publications
58 citations

KTH Royal Institute of Technology
Stockholm, Sweden
2 h-index
2 publications
32 citations
Institut polytechnique de Grenoble
Grenoble, France
2 h-index
5 publications
58 citations
1–8 of 53
MICPRO · 2 publications · 36 citations
2
h-index
2 publications · 34 citations
2
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1 publications · 39 citations
1
h-index
1 publications · 124 citations
1
h-index
1 publications · 60 citations
1
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1–5