Interconnect Verification

Interconnect Verification is a formal method within the domain of Network-on-Chip design that systematically ensures the correctness, reliability, and functional integrity of on-chip communication architectures by validating their structural and behavioral properties against specified requirements.

32

Publications

998

Citations

100

Authors

53

Institutions

Publications per year

2017–2026

2

Authors

100

  1. LP
    Laurence Pierre

    Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France

    3 publications · 54 citations

    3

    h-index

  2. AS
    Amr S. Helmy

    University of Toronto, Canada

    3 publications · 54 citations

    3

    h-index

  3. JS
    Julien Schmaltz

    Radboud University Nijmegen, Netherlands

    3 publications · 71 citations

    3

    h-index

  4. AJ
    Axel Jantsch

    KTH Royal Institute of Technology, Sweden

    2 publications · 32 citations

    2

    h-index

  5. SF
    Steve Furber

    University of Manchester, United Kingdom

    2 publications · 62 citations

    2

    h-index

1–5 of 100

Venues

  1. Microprocessors and Microsystems

    MICPRO · 2 publications · 36 citations

    2

    h-index

  2. 2

    h-index

  3. Applied Physics Letters

    1 publications · 39 citations

    1

    h-index

  4. IEEE Communications Magazine

    1 publications · 124 citations

    1

    h-index

  5. 1

    h-index

1–5