Instruction Pipelining is a processor microarchitecture technique that belongs to the class of instruction-level parallelism methods, distinguished by its organization of instruction execution into a sequential pipeline of stages—such as fetch, decode, execute, and write-back—enabling overlapping processing of multiple instructions to improve throughput while maintaining the illusion of sequential execution.
101
Publications
4.7K
Citations
213
Authors
81
Institutions
Publications per year
2017–2026
5
Publications
101
1–5 of 101
Authors
213
- JE
6
h-index
- GS
6
h-index
- WH
5
h-index
- ES
4
h-index
- NP
4
h-index
1–5 of 213
Institutions
81
University of Wisconsin–Madison
Madison, United States
11 h-index
18 publications
1.2K citations
University of Illinois Urbana-Champaign
Urbana, United States
8 h-index
16 publications
654 citations
Intel (United States)
Santa Clara, United States
7 h-index
9 publications
295 citations
Universitat Politècnica de Catalunya
Barcelona, Spain
4 h-index
8 publications
360 citations
The University of Texas at Austin
Austin, United States
4 h-index
12 publications
1.6K citations
IBM (United States)
Armonk, United States
4 h-index
4 publications
289 citations
University of Manchester
Manchester, United Kingdom
3 h-index
5 publications
151 citations
Stanford University
Stanford, United States
3 h-index
4 publications
93 citations
1–8 of 81
Venues
- ACM SIGARCH Computer Architecture News
8 publications · 892 citations
8
h-index
- IEEE Transactions on Computers
5 publications · 394 citations
5
h-index
- IEEE Micro
4 publications · 71 citations
4
h-index
- Communications of the ACM
2 publications · 62 citations
2
h-index
- Computer
2 publications · 58 citations
2
h-index
1–5