Hardware Dataflow Architectures

Hardware Dataflow Architectures is a computational architecture that belongs to the class of dataflow models of computation, distinguished by its implementation of instruction execution through explicit data dependencies encoded in hardware, where operations are triggered autonomously upon the availability of input data rather than by a centralized control unit.

140

Publications

6.6K

Citations

565

Authors

158

Institutions

Publications per year

2017–2026

44

Authors

565

  1. RG
    Roberto Giorgi

    University of Siena, Italy

    7 publications · 216 citations

    7

    h-index

  2. MR
    Mickaël Raulet

    Institut d'Électronique et des Technologies du numéRique, France

    5 publications · 162 citations

    5

    h-index

  3. TK
    Tushar Krishna

    Georgia Institute of Technology, United States

    5 publications · 638 citations

    5

    h-index

  4. TN
    Tony Nowatzki

    University of Wisconsin–Madison, United States

    4 publications · 283 citations

    4

    h-index

  5. JB
    Jack B. Dennis

    Massachusetts Institute of Technology, United States

    4 publications · 192 citations

    4

    h-index

1–5 of 565

Venues

  1. ACM SIGARCH Computer Architecture News

    7 publications · 147 citations

    7

    h-index

  2. IEEE Transactions on Computers

    4 publications · 231 citations

    4

    h-index

  3. IEEE Access

    3 publications · 41 citations

    3

    h-index

  4. Fall joint computer conference

    Conference · 3 publications · 38 citations

    3

    h-index

  5. IEEE Micro

    3 publications · 58 citations

    3

    h-index

1–5