Hyoukjun Kwon - Concepedia

Author

Hyoukjun Kwon

Georgia Institute of Technology ORCID

Also Known As

Huiyang Zhou, Hyouk Jun Kwon, Hyoukjun Kwon, Intel Litz, Kwon, Hyoukjun

Publications

2.4K

Citations

H-Index

Concepts

All Affiliations

Georgia Institute of Technology Nvidia (United States)Meta (Israel)Sandia National Laboratories Korea Aerospace University

About

Hyoukjun Kwon is an author at Georgia Institute of Technology specializing in computer engineering, engineering, and computer science.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	17	22	2.1K
2	Computer Engineering	17	22	2.1K
3	Computer Science	16	20	2K
4	Data Science	11	11	1.5K
5	Social Sciences	1	1	12

Hyoukjun Kwon

Publications

2.2K

Citations

H-Index

Page 1

	Year	Citations
SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training Eric Qin, Ananda Samajdar, Hyoukjun Kwon, EngineeringMachine LearningHardware AlgorithmComputer ArchitectureKernel Shape	2020	442
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, EngineeringHardware AccelerationAdvanced ComputingEdge ComputingHigh-performance Architecture	2019	280
MAERI Hyoukjun Kwon, Ananda Samajdar, Tushar Krishna Convolutional Neural NetworkDeep Neural NetworksEngineeringMachine LearningData Science	2018	279
Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation Jiaqi Gu, Hyoukjun Kwon, Dilin Wang, 2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR) Convolutional Neural NetworkImage AnalysisMachine VisionData ScienceMachine Learning	2022	229
MAERI Hyoukjun Kwon, Ananda Samajdar, Tushar Krishna ACM SIGPLAN Notices Convolutional Neural NetworkDeep Neural NetworksEngineeringMachine LearningData Science	2018	192
MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings Hyoukjun Kwon, Prasanth Chatarasi, Vivek Sarkar, IEEE Micro EngineeringMachine LearningAdvanced ComputingHardware AlgorithmComputer Architecture	2020	183
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks Lei Yang, Zheyu Yan, Meng Li,	2020	108
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse Jinwoo Kim, Gauthaman Murali, Heechun Park, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Hardware ModelingEngineeringComputer ArchitecturePackage Codesign FlowHardware Architecture	2020	90
Rethinking NoCs for Spatial Neural Network Accelerators Hyoukjun Kwon, Ananda Samajdar, Tushar Krishna EngineeringHardware AccelerationEdge ComputingComputational ParallelismNeural Network	2017	70
Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse Jinwoo Kim, Gauthaman Murali, Heechun Park, EngineeringComputer ArchitectureHardware ArchitectureHardware SecurityAdvanced Packaging (Semiconductors)	2019	53

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