Fault-tolerant Processor Design
Fault-Tolerant Processor Design is a methodology in computer architecture that enables a processor to continue correct operation despite the presence of hardware faults, distinguishing itself by incorporating redundancy, error detection, and recovery mechanisms at the microarchitectural or circuit level to maintain system reliability.
387
Publications
20.3K
Citations
933
Authors
295
Institutions
Publications per year
2017–2026
39
Parents
387
Richard D. Schlichting, Fred B. Schneider · ACM Transactions on Computer Systems · 1983 · 769 citations · Full text
SWIFT: Software Implemented Fault Tolerance
George A. Reis, Jonathan Chang, Neil Vachharajani et al. · 2005 · 710 citations
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Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France
7 publications · 166 citations
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295
University of Michigan
Ann Arbor, United States
21 h-index
70 publications
6.9K citations
University of Illinois Urbana-Champaign
Urbana, United States
17 h-index
49 publications
4.3K citations
Intel (United States)
Santa Clara, United States
15 h-index
57 publications
7.3K citations
Duke University
Durham, United States
13 h-index
35 publications
2.4K citations
Purdue University West Lafayette
West Lafayette, United States
10 h-index
32 publications
2.6K citations
Princeton University
Princeton, United States
9 h-index
22 publications
4.6K citations
Politecnico di Torino
Turin, Italy
9 h-index
26 publications
909 citations
IBM (United States)
Armonk, United States
8 h-index
36 publications
2K citations
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33 publications · 1.7K citations
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11 publications · 743 citations
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11 publications · 296 citations
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9 publications · 1.2K citations
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6 publications · 471 citations
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