Fault-tolerant Processor Design

Fault-Tolerant Processor Design is a methodology in computer architecture that enables a processor to continue correct operation despite the presence of hardware faults, distinguishing itself by incorporating redundancy, error detection, and recovery mechanisms at the microarchitectural or circuit level to maintain system reliability.

387

Publications

20.3K

Citations

933

Authors

295

Institutions

Publications per year

2017–2026

39

Authors

933

  1. DJ
    Daniel J. Sorin

    Duke University, United States

    10 publications · 631 citations

    10

    h-index

  2. RV
    Raoul Velazco

    Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France

    7 publications · 166 citations

    7

    h-index

  3. SM
    Scott Mahlke

    University of Michigan, United States

    7 publications · 299 citations

    7

    h-index

  4. SG
    Shantanu Gupta

    University of Michigan, United States

    7 publications · 392 citations

    7

    h-index

  5. MV
    M. Violante

    Politecnico di Torino, Italy

    6 publications · 186 citations

    6

    h-index

1–5 of 933

Venues

  1. IEEE Transactions on Computers

    33 publications · 1.7K citations

    25

    h-index

  2. IEEE Micro

    11 publications · 743 citations

    11

    h-index

  3. IEEE Transactions on Nuclear Science

    11 publications · 296 citations

    10

    h-index

  4. ACM SIGARCH Computer Architecture News

    9 publications · 1.2K citations

    9

    h-index

  5. Computer

    6 publications · 471 citations

    6

    h-index

1–5