False Path Analysis
False Path Analysis is a timing analysis method that identifies and excludes timing paths in a digital circuit that cannot propagate a signal transition under normal operating conditions, thereby distinguishing spurious timing violations from those that are functionally relevant.
43
Publications
2.2K
Citations
100
Authors
36
Institutions
Publications per year
2017–2026
0
Parents
43
Circuit-based Boolean Reasoning
Andreas Kuehlmann, Malay Ganai, Viresh Paruthi · 2001 · 154 citations
1–5 of 43
100
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University of California, Santa Barbara, United States
3 publications · 387 citations
3
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3
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2
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1–5 of 100
36
IBM (United States)
Armonk, United States
6 h-index
7 publications
931 citations
Cadence Design Systems (United States)
San Jose, United States
5 h-index
6 publications
563 citations
Princeton University
Princeton, United States
4 h-index
4 publications
215 citations

National Taiwan University
Taipei, Taiwan
4 h-index
8 publications
124 citations

Lawrence Berkeley National Laboratory
Berkeley, United States
3 h-index
4 publications
517 citations
University of California, Berkeley
Berkeley, United States
3 h-index
7 publications
486 citations
University of California, Santa Barbara
Santa Barbara, United States
3 h-index
9 publications
1.1K citations
Industrial Technology Research Institute
Hsinchu, Taiwan
2 h-index
2 publications
33 citations
1–8 of 36
8 publications · 733 citations
8
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Conference · 2 publications · 57 citations
2
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1 publications · 148 citations
1
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ITC · 1 publications · 17 citations
1
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Conference · 1 publications · 14 citations
1
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1–5